1. Field of the Invention
Embodiments of the present invention generally relate to an improved implementation of clocked standby mode in a digital circuit.
2. Description of the Related Art
Integrated circuit (IC) devices often operate using various internally generated voltages in an effort to reduce sensitivity to fluctuating external voltage supplies. Each internally generated voltage may also be used to perform different functions required by the IC. A circuit, referred to as a voltage generation circuit, may be used to generate each necessary internal voltage. A typical memory device, such as a dynamic random access memory (DRAM) device may include many such voltage generation circuits, configured to generate a wide range of voltages, which may include voltages that are positive with respect to a ground reference (e.g., a boosted wordline voltage or VPP) and voltages that are negative with respect to a ground reference (e.g., a back-bias voltage, VBB, or negative wordline voltage, VNWL).
Each voltage generation circuit on a given device may consume power while generating a voltage. In order to conserve the power consumed by the IC device, the voltage generation circuit may be placed in a mode (referred to as a standby mode) where the circuit is selectively enabled and disabled. In the standby mode, the voltage generation circuit may be enabled while the required voltage is being used by the IC device. For instance, if the IC device is a memory device, the voltage generation circuit may be enabled just before the memory device is about to use the output of the voltage generation circuit to perform an access (e.g., a read, write, or refresh). While enabled to generate the required voltage, the voltage generation circuit may consume power. When the memory device is not being accessed, the voltage is not required and the voltage generation circuit may be disabled, thus conserving power. Because each access to the memory device may be timed according to a clock (e.g., refresh operations may be triggered by a self-refresh timer), a clock signal may be used to selectively enable and disable the voltage generation circuit just before each access. Accordingly, the standby mode may be referred to as a clocked standby mode (CSM).
FIG. 1 is a block diagram depicting an exemplary memory device 100 which utilizes a clocked standby mode. The memory device 100 may have control circuits 102 used to access one or more memory arrays 104 of the memory device 100. The control circuits 102 may have several internal circuits which may be used to configure and control the memory device. For instance, the control circuits 102 may have a temperature sensor 108 which may be used to measure the temperature of the memory device 100. Based on the measured temperature, an operating characteristic of the memory device 100 (such as a self-refresh period) may be adjusted.
The memory device 100 may contain a reference voltage generator 110 and voltage generation circuit(s) 112. The reference voltage generator 110 may generate an output reference voltage VREF which may be used by the voltage generation circuits 112 to generate output voltages VOUT(s), V1, V2, . . . VX. The output voltages V1, V2, . . . VX and the reference voltage VREF may be supplied to the control circuits 102 and memory arrays 104 of the memory device 100. The reference voltage may be used by the control circuit 102 to access (e.g., read, write or refresh) memory arrays 104. The reference voltage generator 110 and the voltage generation circuit(s) 112 may be selectively enabled and disabled by clocked standby mode controls 114. In some cases, the clocked standby mode controls 114 may be enabled or disabled by the control circuits 102. In other cases, the clocked standby mode controls 114 may be permanently enabled such that an enabling signal is not used, or the clocked standby mode controls 114 may be permanently enabled by blowing a fuse such as a laser fuse or electronically programmable fuse (e-fuse) of the memory device 100.
FIG. 2 is a block diagram depicting exemplary clocked standby mode controls 114 which are used to selectively enable one or more voltage generation circuits 112 and a reference voltage generator 110. The input to the clocked standby mode controls 114 may be a signal to enable the clocked standby mode (referred to as CSM_EN). When CSM_EN is a high logic value, the clocked standby mode may be enabled and a clocked standby mode clock signal (CSM_CLK) may be generated by the clocked standby mode controls 114. In some cases, the clocked standby mode controls 114 may use another clock signal, referred to as a base clock signal (Base_CLK) to generate a clocked standby mode clock signal. The clocked standby mode control signal CSM_CLK may be used to selectively enable and disable the voltage generation circuits 112 and the reference voltage generator 110. When CSM_EN is a certain value (e.g., a low logic value), the clocked standby mode may be disabled, meaning that the voltage generation circuits 112 and the reference voltage generator 110 may constantly generate output voltages and reference voltages. When the clocked standby mode is disabled, the CSM_CLK signal may be set to a constant value (e.g., a low logic value) in order to constantly enable the voltage generation circuits 112 and reference voltage generator 110.
In some cases, enabling and disabling the reference voltage generator 110 and the voltage generation circuits 112 may cause fluctuations in the output reference voltage VREF of the reference voltage generator 110 and output voltages V1, V2, . . . VX of the voltage generation circuits 112. For instance, in some cases, enabling and disabling the reference voltage generator 110 may cause a charge build up in the output reference voltage VREF. Fluctuations in VREF (positive or negative) may in turn cause changes in the output voltages V1, V2, . . . VX of the voltage generation circuits 112. In other cases, even if VREF remains stable, enabling and disabling the voltage generation circuits may cause fluctuations directly in the output voltages V1, V2, . . . VX of the voltage generation circuits 112, regardless of any changes in VREF. Changes in VREF and the output voltages V1, V2, . . . VX of the voltage generation circuits 112 of the memory device 100 may cause the memory device 100 to malfunction. For instance, if one or more of the voltages VREF or V1, V2, . . . VX are used by the control circuits 102 to refresh memory arrays 104 of the memory device 100, changes in the voltages may cause an insufficient refresh of the memory arrays 104 and result in memory loss.
Accordingly, what is needed are improved methods and apparatuses for regulating voltages affected by a clocked standby mode.